GOSBVL SAVPTR * disable interrupts INTOFF * reserve 0x320F nibbles of memory, also P set to 0 LC 0320F GOSBVL MAKE$N * zero out C register C=0.W * C.A = address of beginning of reserved memory CD0EX C+15.A * add 0x0000E to said address ?? why ? * zero out LSN C=0.P * save to R0, accessed in ARM later. R0=C.W * C now contains address of return stack, and D1 contains a word aligned address CD1EX * GOSUBL will put 0x001F at the return stack pointed to by C GOSUBL offset_191F 001F: <6400 bytes of picture code (0x1900)> *offset_191F * C=0x001F C=RSTK * D0=001F D0=C * copy downwards C.A nibbles from * D0 to D1, D0 and D1 will point * to the next locations * Used: A.W C.A P * Use this to move upwards * D0 is locally the picture code * D1 is the word aligned code to move up to LC 03200 GOSBVL MOVEDOWN * zero out lower 5 nibbles of C * makes screen fullscreen? C=0.A BUSCC $33 * writes to saturn IORAM at 00128 * which is the LSBs of vertical line count * writes 2 nibbles, to 00128 and 00129 * which are the LSB and MSB LC 00 D0= 00128 DAT0=C.B GOSUB offset_19D5 1935: e92d4030 stmdb sp!, {r4, r5, lr} 1939: ea000002 b 0x14 193D: 00042825 @ values for LCD controller register 1 1941: 00000d48 1945: 00012210 1949: e3a02673 mov r2, #120586240 @ $07300000 - MMU offset 194D: e5923014 ldr r3, [r2, #20] @ $14 r3=[$7300014] - frame buffer start 1951: e5813934 str r3, [r1, #2356] @ $934 SR1lo 1955: e5923018 ldr r3, [r2, #24] @ $18 r3=[$7300018] - frame buffer end 1959: e5813938 str r3, [r1, #2360] @ $938 SR1hi 195D: e592301c ldr r3, [r2, #28] @ $1C r3=[$730001C] - virtual screen address info @ [21:11] - offset size , difference between address of last @ half word on end of line and next line's first half word @ [10:0] - page width (# of half words), width of view port 1961: e581393c str r3, [r1, #2364] @ $93C SR2lo 1965: e5923000 ldr r3, [r2] @ r3=[$7300000] 1969: e5813940 str r3, [r1, #2368] @ $940 SR2hi -- store LCD controller register info here @ back it up? 196D: e5923010 ldr r3, [r2, #16] @ $10 r3=[$7300016] - lcd control 5 @ [31:17] reserved, should be 0 @ [16:11] TFT only @ [10] INVVCLK , polarity of VCLK active edge, 0 falling, 1 rising @ [9] INVVLINE, VLINE/HSYNC pulse polarity, 0 normal, 1 inverted @ [8] INVVFRAME,VFRAME/VYSNC pulse polarity, 0 normal, 1 inverted @ [7] INVVD, (VD) Video data polarity @ [6] TFT only @ [5] INVPWREN @ [4] TFT only @ [3] PWREN, LCD_PWREN output signal enable/disable @ [2] TFT only @ [1] BSWP byte swap control bit @ [0] HWSWP half-word swap control bit 1971: e5813944 str r3, [r1, #2372] @ $944 SR3lo - back up lcd control 5 data 1975: e51f3040 ldr r3, 0x193D @ r3=00042825 1979: e3c33001 bic r3, r3, #1 @ r3=00042824 ; this sets the LCD controller to ; 1 0000101000 0 01 0010 0 ; 0 - turn off display ; 0010 - 16 level gray display ; 01 - 4 bit single scan LCD ; 0 - toggle rate ;[17:8]- clock rate ; 1 - LINECNT 197D: e5823000 str r3, [r2] @ [$7300000]=00042824 1981: e591392c ldr r3, [r1, #2348] @ $92C SR0lo - load address of beginning of picture data 1985: e1a04623 mov r4, r3, lsr #12 @ shift right 12 bits to get to correct bank 1989: e7914104 ldr r4, [r1, r4, lsl #2] @ shift left 2 bits to word align it, add r1 offset 198D: e3c33aff bic r3, r3, #1044480 @ $FF000 , offset for inside bank 1991: e08430a3 add r3, r4, r3, lsr #1 @ nibble offset 1995: e1a030a3 mov r3, r3, lsr #1 1999: e5823014 str r3, [r2, #20] @ $14 [$73000014]=r3 - set frame buffer beginning 199D: e3c336fe bic r3, r3, #266338304 @ 00001111111000000000000000000000 19A1: e3c3320f bic r3, r3, #-268435456 @ 11110000000000000000000000000000 @ $FFE00000 19A5: e51f406c ldr r4, 0x1941 @ r4=$d48=#3400 19A9: e0833004 add r3, r3, r4 @ frame buffer beginning + 3400, strip bits 29:21 @ LINEVAL=80-1 = 0x4f @ PAGEWIDTH = 160*4/16=40=0x28 @ OFFSIZE = 0 @ LCDBANK = @ LCDBASEU = [r2, #20] @ b/c they are not used in $18 19AD: e5823018 str r3, [r2, #24] @ [$7300018]=r3 19B1: e3a03028 mov r3, #40 @ $28 19B5: e582301c str r3, [r2, #28] @ [$730001C]=r3=$28=#40 , 40 half words per line, 160 pixels 19B9: e51f307c ldr r3, 0x10 @ r3=0x12210 19BD: e582304c str r3, [r2, #76] @ [$730004C]=r3=12210 -- dithering mode, must be 0 or 12210 19C1: e3a03000 mov r3, #0 19C5: e5823010 str r3, [r2, #16] @ [$7300010]=r3=$0 --- clear lcd register 5 19C9: e51f3094 ldr r3, 0x8 19CD: e5823000 str r3, [r2] @ [$7300000]=r3=42825 - re-enable LCD 19D1: e8bd8030 ldmia sp!, {r4, r5, pc} * calls ARM code at 1935 offset_19D5: C=RSTK D0=C D1= 80100 LC 00140 GOSBVL MOVEDOWN LC 80100 BUSCC ARMSAT * wait for cleared kb, then continue on kb press LC 0FF OUT=C { GOSBVL CINRTN ?C#0.B UP } { GOSBVL CINRTN ?C=0.B UP } GOSUB offset_1A56 19FA: e92d4030 stmdb sp!, {r4, r5, lr} 19FE: ea000001 b 0x1A0A 1A02: 00042821 1A06: 00000352 1A0A: e3a02673 mov r2, #120586240 @ $7300000 hex 1A0E: e51f3014 ldr r3, 0x1A02 @ r3=00042821 1A12: e3c33001 bic r3, r3, #1 @ r3=00042820 1A16: e5823000 str r3, [r2] @ [$7300000]=00042820 -- turn LCD off 1A1A: e3a03e13 mov r3, #304 @ $130 hex r3=00000130 1A1E: e2833202 add r3, r3, #536870912 @ $20000000 hex r3=20000130 1A22: e5823014 str r3, [r2, #20] @ $14 -- restore frame buffer location 1A26: e51f4028 ldr r4, 0x1A06 @ r4=00000352 1A2A: e0833004 add r3, r3, r4 @ r3=20000482 1A2E: e5823018 str r3, [r2, #24] @ -- restore frame buffer end location 1A32: e3a0300a mov r3, #10 @ $0A 1A36: e582301c str r3, [r2, #28] @ $1C -- set page width to 10 half words, 160 monochrome pix 1A3A: e3a03000 mov r3, #0 1A3E: e582304c str r3, [r2, #76] @ $4C -- set dither mode to 0 1A42: e3a03002 mov r3, #2 1A46: e5823010 str r3, [r2, #16] @ $10 -- enable byte swap control bit 1A4A: e51f3050 ldr r3, 0x1A02 1A4E: e5823000 str r3, [r2] @ enable LCD 1A52: e8bd8030 ldmia sp!, {r4, r5, pc} *offset_1A56 C=RSTK D0=C D1= 80100 LC 000B8 GOSBVL MOVEDOWN LC 80100 BUSCC ARMSAT LC 00010 BUSCC SETLNED LC 37 D0= 00128 DAT0=C.B GOVLNG GETPTRLOOP