EMU49+

The ultimate HP49G+ emulator

(not yet done :)

 

Informations :

For the moment, we only have few informations about the HP49G+. You can have these informations by following these links :

 

You can also get informations with :

 

You can help us by giving informations to mwyann.r.e.m.o.v.e.s.p.a.m@hotmail.com

You can also look at our information page

Implementation :

EMU49+ is a future program that should emualte the HP49G+ calculator. But, before, we must simulate the ARM chipset. So, here is my program, called EmuPlus : emuplus.tar.gz (works with cygwin dll : cygwin1.dll.gz )


You can test it with the "tst.bin" file provided. It runs a simple loop :

begin mov R0, #5
mov R1,#32
str R0,[R1]
mov R0,#0
ldr R0,[R1]
loop subs R0, R0, #1
bne loop
b begin

Well working : B BL AND EOR SUB RSB ADD ADC SBC RSC TST TEQ CMP CMN ORR MOV BIC MVN LDR STR
Pretty well working :
Not working yet : MRS MSR MUL MLA LDM STM SWP SWI CDP LDC STC MRC MCR BX

ADC Add with carry Rd: = Rn + Op2 + Carry
ADD Add Rd: = Rn + Op2
AND AND Rd: = Rn AND Op2
B Branch R15: = address
BIC Bit Clear Rd: = Rn AND NOT Op2
BL Branch with Link R14: = R15, R15: = address

BX Branch and Exchange R15: = Rn, T bit: = Rn[0]
CDP Coprocessor Data Processing (Coprocessor-specific)
CMN Compare Negative CPSR flags: = Rn + Op2
CMP Compare CPSR flags: = Rn - Op2
EOR Exclusive OR Rd: = (Rn AND NOT Op2) OR (Op2 AND NOT Rn)

LDC Load coprocessor from memory Coprocessor load
LDM Load multiple registers Stack manipulation (Pop)
LDR Load register from memory Rd: = (address)
MCR Move CPU register to coprocessor register cRn: = rRn {[op]cRm}
MLA Multiply Accumulate Rd: = (Rm Rs) + Rn
MOV Move register or constant Rd: = Op2
MRC Move from coprocessor register to CPU register rRn: = cRn {[op]cRm}
MRS Move PSR status/flags to register Rn: = PSR
MSR Move register to PSR status/flags PSR: = Rm
MUL Multiply Rd: = Rm Rs
MVN Move negative register Rd: = 0 FFFFFFFF EOR Op2
ORR OR Rd: = Rn OR Op2
RSB Reverse Subtract Rd: = Op2 - Rn
RSC Reverse Subtract with Carry Rd: = Op2 - Rn - 1 + Carry
SBC Subtract with Carry Rd: = Rn - Op2 - 1 + Carry

STC Store coprocessor register to memory address: = CRn
STM Store Multiple Stack manipulation (Push)
STR Store register to memory [address]: = Rd
SUB Subtract Rd: = Rn - Op2

SWI Software Interrupt OS call
SWP Swap register with memory Rd: = [Rn], [Rn] := Rm
TEQ Test bitwise equality CPSR flags: = Rn EOR Op2
TST Test bits CPSR flags: = Rn AND Op2



It is multi-threaded. Here, I can get 58 Mhz at least (with my intel celeron 2,8 Ghz).

Here you can get the main schematic : emuplus.pdf . Personnaly, I will work on the 2nd one.